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* Support dynamic registers, support register offsets and multiregisters ↵Suren A. Chilingaryan2011-07-091-6/+6
| | | | (bitmasks), list NWL DMA registers
* Support FIFO reading/writting, code restructurization, few fixesSuren A. Chilingaryan2011-07-061-2/+0
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* Move to new FPGA designroot2011-06-161-2/+3
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* 32 bit fixSuren A. Chilingaryan2011-06-071-1/+1
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* Support for FPGA registersSuren A. Chilingaryan2011-03-091-0/+39