From c95df4d43738e1597c348bc7f98ff2902574d720 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 16 Jun 2011 01:26:14 +0200 Subject: Move to new FPGA design --- ipecamera/model.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'ipecamera/model.c') diff --git a/ipecamera/model.c b/ipecamera/model.c index c258a32..23715e3 100644 --- a/ipecamera/model.c +++ b/ipecamera/model.c @@ -31,8 +31,8 @@ int ipecamera_read(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcil assert(addr < 128); - wr = pcilib_resolve_register_address(ctx, bank->write_addr); - rd = pcilib_resolve_register_address(ctx, bank->read_addr); + wr = pcilib_resolve_register_address(ctx, bank->bar, bank->write_addr); + rd = pcilib_resolve_register_address(ctx, bank->bar, bank->read_addr); if ((!rd)||(!wr)) { pcilib_error("Error resolving addresses of read & write registers"); return PCILIB_ERROR_INVALID_ADDRESS; @@ -121,8 +121,8 @@ int ipecamera_write(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pci assert(addr < 128); assert(value < 256); - wr = pcilib_resolve_register_address(ctx, bank->write_addr); - rd = pcilib_resolve_register_address(ctx, bank->read_addr); + wr = pcilib_resolve_register_address(ctx, bank->bar, bank->write_addr); + rd = pcilib_resolve_register_address(ctx, bank->bar, bank->read_addr); if ((!rd)||(!wr)) { pcilib_error("Error resolving addresses of read & write registers"); return PCILIB_ERROR_INVALID_ADDRESS; -- cgit v1.2.3