Fix #2: reset frame request and flush at the end

This is an intermediate fix proposed by Michele but not really solving the
underlying issue of the FPGA getting stuck. The fix consists of two separate
solutions:

1. In case we encounter an error while grabbing we reset the command queue on
   the FPGA (i.e. flipping third bit on the control register).

2. We read all stale data from the FPGA with a timeout now. Before it was still
   possible to have stale data in the DDR thus corrupting subsequent data reads.

0 files changed, 0 insertions, 0 deletions