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| author | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-18 16:42:51 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-18 16:42:51 +0200 |
| commit | 9e424252a35879f121e7ea4531a9ab3dda56d595 (patch) | |
| tree | 2cf3dfeceb67eee989a6cc4b20f639baf68748f8 /dma/nwl_engine.c | |
| parent | e9904116a5b39e47744fb39cc5aad574c8bee03f (diff) | |
| download | ipecamera-9e424252a35879f121e7ea4531a9ab3dda56d595.tar.gz ipecamera-9e424252a35879f121e7ea4531a9ab3dda56d595.tar.bz2 ipecamera-9e424252a35879f121e7ea4531a9ab3dda56d595.tar.xz ipecamera-9e424252a35879f121e7ea4531a9ab3dda56d595.zip | |
IRQ acknowledgement support in the engine API
Diffstat (limited to 'dma/nwl_engine.c')
| -rw-r--r-- | dma/nwl_engine.c | 21 |
1 files changed, 4 insertions, 17 deletions
diff --git a/dma/nwl_engine.c b/dma/nwl_engine.c index 669dbbd..277ad23 100644 --- a/dma/nwl_engine.c +++ b/dma/nwl_engine.c @@ -77,12 +77,7 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { if (info->reused) { info->preserve = 1; - // Acknowledge asserted engine interrupts - nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); - if (val & DMA_ENG_INT_ACTIVE_MASK) { - val |= DMA_ENG_ALLINT_MASK; - nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - } + dma_nwl_acknowledge_irq(ctx, PCILIB_DMA_IRQ, dma); #ifdef NWL_GENERATE_DMA_IRQ dma_nwl_enable_engine_irq(ctx, dma); @@ -131,11 +126,7 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { return PCILIB_ERROR_TIMEOUT; } - // Acknowledge asserted engine interrupts - if (val & DMA_ENG_INT_ACTIVE_MASK) { - val |= DMA_ENG_ALLINT_MASK; - nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - } + dma_nwl_acknowledge_irq(ctx, PCILIB_DMA_IRQ, dma); ring_pa = pcilib_kmem_get_pa(ctx->pcilib, info->ring); nwl_write_register(ring_pa, ctx, info->base_addr, REG_DMA_ENG_NEXT_BD); @@ -206,12 +197,8 @@ int dma_nwl_stop_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { nwl_write_register(ring_pa, ctx, info->base_addr, REG_SW_NEXT_BD); } } - - // Acknowledge asserted engine interrupts - if (val & DMA_ENG_INT_ACTIVE_MASK) { - val |= DMA_ENG_ALLINT_MASK; - nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - } + + dma_nwl_acknowledge_irq(ctx, PCILIB_DMA_IRQ, dma); if (info->preserve) { flags = PCILIB_KMEM_FLAG_REUSE; |