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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-03-29 18:05:58 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-03-29 18:05:58 +0200 |
| commit | adb36212be886985dbaf397d7d2dd875b3d4aab8 (patch) | |
| tree | 292b252b22f823eb4eb8753c7d437b723e23a85b /ipecamera/ipecamera.c | |
| parent | b222af943c405df509eb9df084d203da4fbd324e (diff) | |
| download | ipecamera-adb36212be886985dbaf397d7d2dd875b3d4aab8.tar.gz ipecamera-adb36212be886985dbaf397d7d2dd875b3d4aab8.tar.bz2 ipecamera-adb36212be886985dbaf397d7d2dd875b3d4aab8.tar.xz ipecamera-adb36212be886985dbaf397d7d2dd875b3d4aab8.zip | |
Fix frame size computation in ipecamera and few debuging options
Diffstat (limited to 'ipecamera/ipecamera.c')
| -rw-r--r-- | ipecamera/ipecamera.c | 36 |
1 files changed, 27 insertions, 9 deletions
diff --git a/ipecamera/ipecamera.c b/ipecamera/ipecamera.c index 1b3d305..f54c29d 100644 --- a/ipecamera/ipecamera.c +++ b/ipecamera/ipecamera.c @@ -97,6 +97,7 @@ pcilib_context_t *ipecamera_init(pcilib_t *pcilib) { FIND_REG(status_reg, "fpga", "status"); FIND_REG(control_reg, "fpga", "control"); + FIND_REG(status2_reg, "fpga", "status2"); FIND_REG(status3_reg, "fpga", "status3"); FIND_REG(n_lines_reg, "cmosis", "cmosis_number_lines"); @@ -304,8 +305,9 @@ int ipecamera_start(pcilib_context_t *vctx, pcilib_event_t event_mask, pcilib_ev if (value&0x1000) ctx->fr_mode = 1; else { ctx->fr_mode = 0; - CHECK_STATUS_REG(); - if (err) return err; + +// CHECK_STATUS_REG(); +// if (err) return err; } ctx->event_id = 0; @@ -659,12 +661,28 @@ int ipecamera_trigger(pcilib_context_t *vctx, pcilib_event_t event, size_t trigg return PCILIB_ERROR_BUSY; } */ -/* - do { - usleep(10); - GET_REG(status3_reg, value); - } while (value&0x20000000); -*/ + + GET_REG(status2_reg, value); + if (value&0x40000000) { +// printf("%x\n", value); +// GET_REG(status3_reg, value); +// printf("3: %x\n", value); +// GET_REG(status_reg, value); +// printf("1: %x\n", value); + +#ifdef IPECAMERA_TRIGGER_WAIT_IDLE + if (IPECAMERA_TRIGGER_WAIT_IDLE) { + struct timeval deadline; + pcilib_calc_deadline(&deadline, IPECAMERA_TRIGGER_WAIT_IDLE); + do { + usleep(IPECAMERA_READ_STATUS_DELAY); + GET_REG(status2_reg, value); + } while ((value&0x40000000)&&(pcilib_calc_time_to_deadline(&deadline) > 0)); + } + if (value&0x40000000) +#endif /* IPECAMERA_TRIGGER_WAIT_IDLE */ + return PCILIB_ERROR_BUSY; + } GET_REG(control_reg, value); SET_REG(control_reg, value|IPECAMERA_FRAME_REQUEST); @@ -672,7 +690,7 @@ int ipecamera_trigger(pcilib_context_t *vctx, pcilib_event_t event, size_t trigg //CHECK_REG(status_reg, IPECAMERA_EXPECTED_STATUS); SET_REG(control_reg, value); - + // We need to compute it differently, on top of that add exposure time and the time FPGA takes to read frame from CMOSIS pcilib_calc_deadline(&ctx->next_trigger, IPECAMERA_NEXT_FRAME_DELAY); return 0; |