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* First iteration of work to preserve DMA state between executionsSuren A. Chilingaryan2011-07-141-2/+6
* IRQ support in NWL DMA engineSuren A. Chilingaryan2011-07-111-11/+0
* Support dynamic registers, support register offsets and multiregisters (bitma...Suren A. Chilingaryan2011-07-091-8/+13
* Support FIFO reading/writting, code restructurization, few fixesSuren A. Chilingaryan2011-07-061-492/+48
* North West Logick DMA implementationroot2011-07-041-90/+21
* DMA engine initialization and basic intrastructure for DMA read/writeroot2011-06-181-0/+38
* Enumerate DMA enginesroot2011-06-171-14/+30
* A bit of DMA infrastructureroot2011-06-161-11/+29
* Move to new FPGA designroot2011-06-161-44/+103
* Some improvements in error handlingSuren A. Chilingaryan2011-05-031-12/+40
* Introduce pcilib_context_t type instead pointer to voidSuren A. Chilingaryan2011-04-141-1/+1
* Accept timeout parameter to get_next_event callSuren A. Chilingaryan2011-04-141-2/+2
* Support non-callback way of getting eventsSuren A. Chilingaryan2011-04-141-0/+18
* Really fix setting registers with access mode equal to 32 (size of pcilib_reg...Suren A. Chilingaryan2011-04-131-2/+2
* Allow access to implementation context and provide call to set size of intern...Suren A. Chilingaryan2011-04-121-0/+3
* Prototype of IPECamera image protocolSuren A. Chilingaryan2011-04-121-4/+33
* Infrastructure for event APISuren A. Chilingaryan2011-04-121-11/+276
* Fix exiting on warningsSuren A. Chilingaryan2011-03-251-2/+4
* Set warning handlerMatthias Vogelgesang2011-03-141-1/+2
* Correctly detect model in pci.cSuren A. Chilingaryan2011-03-111-11/+18
* Provide single header for librarySuren A. Chilingaryan2011-03-091-2/+0
* Support for FPGA registersSuren A. Chilingaryan2011-03-091-2/+2
* Support writting and reading of register rangesSuren A. Chilingaryan2011-03-091-3/+27
* Better handling of register banksSuren A. Chilingaryan2011-03-091-20/+62
* Initial support of IPECamera protocolSuren A. Chilingaryan2011-03-081-70/+324
* Initial support for registers, infrastructure onlySuren A. Chilingaryan2011-02-181-459/+55
* Print new lineSuren A. Chilingaryan2011-02-131-1/+1
* Print a bit more detailsSuren A. Chilingaryan2011-02-131-15/+40
* Initial importSuren A. Chilingaryan2011-02-131-0/+569
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