IPEDMA Update

1 files changed, 14 insertions, 6 deletions

diff --git a/dma/ipe_private.h b/dma/ipe_private.h
index 5054a58..fdc2d83 100644
--- a/dma/ipe_private.h
+++ b/dma/ipe_private.h
@@ -10,8 +10,6 @@
 
 #define IPEDMA_STREAMING_MODE				/**< Enables streaming DMA operation mode instead of ring-buffer, the page is written once and forgotten and need to be pushed in queue again */
 //#define IPEDMA_STREAMING_CHECKS				/**< Enables status checks in streaming mode (it will cause _significant_ performance penalty, max ~ 2 GB/s) */
-#define IPEDMA_PAGE_SIZE		4096
-#define IPEDMA_DMA_PAGES		1024		/**< number of DMA pages in the ring buffer to allocate */
 #define IPEDMA_DMA_PROGRESS_THRESHOLD	1		/**< how many pages the DMA engine should fill before reporting progress */
 #define IPEDMA_DESCRIPTOR_SIZE		128
 #define IPEDMA_DESCRIPTOR_ALIGNMENT	64
@@ -21,16 +19,13 @@
 //#define IPEDMA_DETECT_PACKETS				/**< Using empty_deceted flag */
 #define  IPEDMA_SUPPORT_EMPTY_DETECTED			/**< Avoid waiting for data when empty_detected flag is set in hardware */
 
-#define IPEDMA_DMA_TIMEOUT 		100000		/**< us, overrides PCILIB_DMA_TIMEOUT (actual hardware timeout is 50ms according to Lorenzo) */
-#define IPEDMA_RESET_DELAY		100000		/**< Sleep between accessing DMA control and reset registers */
-#define IPEDMA_ADD_PAGE_DELAY		1000		/**< Delay between submitting successive DMA pages into IPEDMA_REG_PAGE_ADDR register */
-#define IPEDMA_NODATA_SLEEP		10		/**< To keep CPU free */
 
 #define IPEDMA_REG_RESET		0x00
 #define IPEDMA_REG_CONTROL		0x04
 #define IPEDMA_REG_TLP_SIZE		0x0C
 #define IPEDMA_REG_TLP_COUNT		0x10
 #define IPEDMA_REG_PCIE_GEN		0x18
+#define IPEDMA_REG_VERSION		0x20
 #define IPEDMA_REG_PAGE_ADDR		0x50
 #define IPEDMA_REG_UPDATE_ADDR		0x54
 #define IPEDMA_REG_LAST_READ		0x58		/**< In streaming mode, we can use it freely to track current status */
@@ -38,9 +33,16 @@
 #define IPEDMA_REG_UPDATE_THRESHOLD	0x60
 #define IPEDMA_REG_STREAMING_STATUS	0x68
 
+#define IPEDMA_FLAG_NOSYNC		0x01		/**< Do not call kernel space for page synchronization */
+#define IPEDMA_FLAG_NOSLEEP		0x02		/**< Do not sleep in the loop while waiting for the data */
+
 #define IPEDMA_MASK_PCIE_GEN		0xF
 #define IPEDMA_MASK_STREAMING_MODE	0x10
 
+#define IPEDMA_RESET_DELAY		10000		/**< Sleep between accessing DMA control and reset registers */
+#define IPEDMA_ADD_PAGE_DELAY		1000		/**< Delay between submitting successive DMA pages into IPEDMA_REG_PAGE_ADDR register */
+#define IPEDMA_NODATA_SLEEP		100		/**< To keep CPU free, in nanoseconds */
+
 
 #define WR(addr, value) { *(uint32_t*)(ctx->base_addr + addr) = value; }
 #define RD(addr, value) { value = *(uint32_t*)(ctx->base_addr + addr); }
@@ -59,6 +61,7 @@ struct ipe_dma_s {
     pcilib_irq_type_t irq_preserve;	/**< indicates that IRQs should not be disabled during clean-up */
     int irq_started;			/**< indicates that IRQ subsystem is initialized (detecting which types should be preserverd) */    
 
+    uint32_t version;			/**< hardware version */
     int started;			/**< indicates that DMA buffers are initialized and reading is allowed */
     int writting;			/**< indicates that we are in middle of writting packet */
     int reused;				/**< indicates that DMA was found intialized, buffers were reused, and no additional initialization is needed */
@@ -66,6 +69,11 @@ struct ipe_dma_s {
     int mode64;				/**< indicates 64-bit operation mode */
     int streaming;			/**< indicates if DMA is operating in streaming or ring-buffer mode */
 
+    uint32_t dma_flags;			/**< Various operation flags, see IPEDMA_FLAG_* */
+    size_t dma_timeout;			/**< DMA timeout,IPEDMA_DMA_TIMEOUT is used by default */
+    size_t dma_pages;			/**< Number of DMA pages in ring buffer to allocate */
+    size_t dma_page_size;		/**< Size of a single DMA page */
+
     pcilib_kmem_handle_t *desc;		/**< in-memory status descriptor written by DMA engine upon operation progess */
     pcilib_kmem_handle_t *pages;	/**< collection of memory-locked pages for DMA operation */