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authorSuren A. Chilingaryan <csa@suren.me>2015-05-06 05:46:01 +0200
committerSuren A. Chilingaryan <csa@suren.me>2015-05-06 05:46:01 +0200
commitb9a1af8a3b03a5e8575d87c3593a5931cd0e7a8c (patch)
treea0e73734d597ab1ab4a1d8a6393923d7e8b0914b /dma/ipe_private.h
parent53582e958d727e06648743e505862f9df11bbb35 (diff)
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Add fields reporting consumed buffers and space to the dma_engine_status and provide better ipedma benchmarking
Diffstat (limited to 'dma/ipe_private.h')
-rw-r--r--dma/ipe_private.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/dma/ipe_private.h b/dma/ipe_private.h
index 82ea73a..1fb4e9e 100644
--- a/dma/ipe_private.h
+++ b/dma/ipe_private.h
@@ -7,12 +7,15 @@
#define IPEDMA_CORES 1
#define IPEDMA_TLP_SIZE 32
#define IPEDMA_PAGE_SIZE 4096
-#define IPEDMA_DMA_PAGES 16 /**< number of DMA pages in the ring buffer to allocate */
+#define IPEDMA_DMA_PAGES 32 /**< number of DMA pages in the ring buffer to allocate */
#define IPEDMA_DMA_PROGRESS_THRESHOLD 1 /**< how many pages the DMA engine should fill before reporting progress */
#define IPEDMA_DESCRIPTOR_SIZE 128
#define IPEDMA_DESCRIPTOR_ALIGNMENT 64
#define IPEDMA_BUG_LAST_READ /**< We should forbid writting the second last available DMA buffer (the last is forbidden by design) */
+#define IPEDMA_RESET_DELAY 100000 /**< Sleep between accessing DMA control and reset registers */
+#define IPEDMA_ADD_PAGE_DELAY 1000 /**< Delay between submitting successive DMA pages into IPEDMA_REG_PAGE_ADDR register */
+#define IPEDMA_NODATA_SLEEP 10 /**< To keep CPU free */
//#define IPEDMA_BUG_DMARD /**< No register read during DMA transfer */
//#define IPEDMA_DETECT_PACKETS /**< Using empty_deceted flag */
@@ -30,6 +33,9 @@
#define IPEDMA_REG_UPDATE_THRESHOLD 0x60
+#define WR(addr, value) { *(uint32_t*)(ctx->base_addr + addr) = value; }
+#define RD(addr, value) { value = *(uint32_t*)(ctx->base_addr + addr); }
+
typedef struct ipe_dma_s ipe_dma_t;