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author | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-12 14:51:11 +0200 |
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committer | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-12 14:51:11 +0200 |
commit | 6c922712fd8ee7e75a1b45c4980be22d36d0d1d9 (patch) | |
tree | f10f58ea417b269447f3c3db805e7a5269e845cf /dma/nwl.h | |
parent | 493958c9cf11eaa25251d91e9ecab9a28bd6d68f (diff) | |
download | pcitool-6c922712fd8ee7e75a1b45c4980be22d36d0d1d9.tar.gz pcitool-6c922712fd8ee7e75a1b45c4980be22d36d0d1d9.tar.bz2 pcitool-6c922712fd8ee7e75a1b45c4980be22d36d0d1d9.tar.xz pcitool-6c922712fd8ee7e75a1b45c4980be22d36d0d1d9.zip |
Another reorganization of NWL sources
Diffstat (limited to 'dma/nwl.h')
-rw-r--r-- | dma/nwl.h | 19 |
1 files changed, 17 insertions, 2 deletions
@@ -1,14 +1,29 @@ #ifndef _PCILIB_NWL_H #define _PCILIB_NWL_H +typedef struct nwl_dma_s nwl_dma_t; +typedef struct pcilib_nwl_engine_description_s pcilib_nwl_engine_description_t; + +#define NWL_DMA_IRQ_SOURCE 0 + +#define NWL_XAUI_ENGINE 0 +#define NWL_XRAWDATA_ENGINE 1 +#define NWL_FIX_EOP_FOR_BIG_PACKETS // requires precise sizes in read requests +//#define NWL_GENERATE_DMA_IRQ + +#define PCILIB_NWL_ALIGNMENT 64 // in bytes +#define PCILIB_NWL_DMA_DESCRIPTOR_SIZE 64 // in bytes +#define PCILIB_NWL_DMA_PAGES 512 // 1024 + #include "nwl_dma.h" #include "nwl_irq.h" #include "nwl_register.h" +#include "nwl_engine.h" #define nwl_read_register(var, ctx, base, reg) pcilib_datacpy(&var, base + reg, 4, 1, ctx->dma_bank->raw_endianess) #define nwl_write_register(var, ctx, base, reg) pcilib_datacpy(base + reg, &var, 4, 1, ctx->dma_bank->raw_endianess) -typedef struct { +struct pcilib_nwl_engine_description_s { pcilib_dma_engine_description_t desc; char *base_addr; @@ -20,7 +35,7 @@ typedef struct { int started; /**< indicates that DMA buffers are initialized and reading is allowed */ int writting; /**< indicates that we are in middle of writting packet */ int preserve; /**< indicates that DMA should not be stopped during clean-up */ -} pcilib_nwl_engine_description_t; +}; struct nwl_dma_s { |