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| author | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-17 14:54:21 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-17 14:54:21 +0200 |
| commit | 4fe2032eca29d7f7a0fdf23ef0f3d2c324aeeba2 (patch) | |
| tree | 953edec5c531f34bc5168f54e2ea168515ce29ed /dma | |
| parent | 06b3e35cc964d4735bd62d293b9d51f689545f97 (diff) | |
| download | pcitool-4fe2032eca29d7f7a0fdf23ef0f3d2c324aeeba2.tar.gz pcitool-4fe2032eca29d7f7a0fdf23ef0f3d2c324aeeba2.tar.bz2 pcitool-4fe2032eca29d7f7a0fdf23ef0f3d2c324aeeba2.tar.xz pcitool-4fe2032eca29d7f7a0fdf23ef0f3d2c324aeeba2.zip | |
Stop only started engines
Diffstat (limited to 'dma')
| -rw-r--r-- | dma/nwl_engine.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/dma/nwl_engine.c b/dma/nwl_engine.c index f5ca30e..2e7ae7e 100644 --- a/dma/nwl_engine.c +++ b/dma/nwl_engine.c @@ -65,10 +65,13 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { if (info->started) return 0; - // This will only successed if there are no parallel access to DMA engine err = dma_nwl_allocate_engine_buffers(ctx, info); - if (err) return err; + if (err) { + info->started = 1; + dma_nwl_stop_engine(ctx, dma); + return err; + } if (info->reused) { info->preserve = 1; @@ -85,7 +88,11 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { } else { // Disable IRQs err = dma_nwl_disable_engine_irq(ctx, dma); - if (err) return err; + if (err) { + info->started = 1; + dma_nwl_stop_engine(ctx, dma); + return err; + } // Disable Engine & Reseting val = DMA_ENG_DISABLE|DMA_ENG_USER_RESET; @@ -99,6 +106,9 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { if (val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET)) { pcilib_error("Timeout during reset of DMA engine %i", info->desc.addr); + + info->started = 1; + dma_nwl_stop_engine(ctx, dma); return PCILIB_ERROR_TIMEOUT; } @@ -113,6 +123,9 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { if (val & DMA_ENG_RESET) { pcilib_error("Timeout during reset of DMA engine %i", info->desc.addr); + + info->started = 1; + dma_nwl_stop_engine(ctx, dma); return PCILIB_ERROR_TIMEOUT; } @@ -167,6 +180,8 @@ int dma_nwl_stop_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { pcilib_nwl_engine_description_t *info = ctx->engines + dma; char *base = ctx->engines[dma].base_addr; + if (!info->started) return 0; + info->started = 0; err = dma_nwl_disable_engine_irq(ctx, dma); |