1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
|
#define _BSD_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/time.h>
#include "pci.h"
#include "pcilib.h"
#include "error.h"
#include "tools.h"
#include "nwl.h"
#include "nwl_defines.h"
int dma_nwl_start_loopback(nwl_dma_t *ctx, pcilib_dma_direction_t direction, size_t packet_size) {
uint32_t val;
ctx->loopback_started = 1;
dma_nwl_stop_loopback(ctx);
val = packet_size;
nwl_write_register(val, ctx, ctx->base_addr, PKT_SIZE_ADDRESS);
if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) {
switch (direction) {
case PCILIB_DMA_BIDIRECTIONAL:
val = LOOPBACK;
nwl_write_register(val, ctx, ctx->base_addr, TX_CONFIG_ADDRESS);
break;
case PCILIB_DMA_TO_DEVICE:
return -1;
case PCILIB_DMA_FROM_DEVICE:
val = PKTGENR;
nwl_write_register(val, ctx, ctx->base_addr, RX_CONFIG_ADDRESS);
break;
}
}
ctx->loopback_started = 1;
return 0;
}
int dma_nwl_stop_loopback(nwl_dma_t *ctx) {
uint32_t val = 0;
if (!ctx->loopback_started) return 0;
/* Stop in any case, otherwise we can have problems in benchmark due to
engine initialized in previous run, and benchmark is only actual usage.
Otherwise, we should detect current loopback status during initialization */
if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) {
nwl_write_register(val, ctx, ctx->base_addr, TX_CONFIG_ADDRESS);
nwl_write_register(val, ctx, ctx->base_addr, RX_CONFIG_ADDRESS);
}
ctx->loopback_started = 0;
return 0;
}
double dma_nwl_benchmark(pcilib_dma_context_t *vctx, pcilib_dma_engine_addr_t dma, uintptr_t addr, size_t size, size_t iterations, pcilib_dma_direction_t direction) {
int iter, i;
int res;
int err;
size_t bytes;
uint32_t val;
uint32_t *buf, *cmp;
const char *error = NULL;
pcilib_register_value_t regval;
size_t us = 0;
struct timeval start, cur;
nwl_dma_t *ctx = (nwl_dma_t*)vctx;
pcilib_dma_engine_t readid = pcilib_find_dma_by_addr(ctx->pcilib, PCILIB_DMA_FROM_DEVICE, dma);
pcilib_dma_engine_t writeid = pcilib_find_dma_by_addr(ctx->pcilib, PCILIB_DMA_TO_DEVICE, dma);
char *read_base = ctx->engines[readid].base_addr;
char *write_base = ctx->engines[writeid].base_addr;
if (size%sizeof(uint32_t)) size = 1 + size / sizeof(uint32_t);
else size /= sizeof(uint32_t);
// Not supported
if (direction == PCILIB_DMA_TO_DEVICE) return -1.;
else if ((direction == PCILIB_DMA_FROM_DEVICE)&&(ctx->type != PCILIB_DMA_MODIFICATION_DEFAULT)) return -1.;
// Stop Generators and drain old data
if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) dma_nwl_stop_loopback(ctx);
// dma_nwl_stop_engine(ctx, readid); // DS: replace with something better
__sync_synchronize();
err = pcilib_skip_dma(ctx->pcilib, readid);
if (err) {
pcilib_error("Can't start benchmark, devices continuously writes unexpected data using DMA engine");
return err;
}
#ifdef NWL_GENERATE_DMA_IRQ
dma_nwl_enable_engine_irq(ctx, readid);
dma_nwl_enable_engine_irq(ctx, writeid);
#endif /* NWL_GENERATE_DMA_IRQ */
dma_nwl_start_loopback(ctx, direction, size * sizeof(uint32_t));
// Allocate memory and prepare data
buf = malloc(size * sizeof(uint32_t));
cmp = malloc(size * sizeof(uint32_t));
if ((!buf)||(!cmp)) {
if (buf) free(buf);
if (cmp) free(cmp);
return -1;
}
//#ifdef DEBUG_HARDWARE
if (ctx->type == PCILIB_NWL_MODIFICATION_IPECAMERA) {
pcilib_write_register(ctx->pcilib, NULL, "control", 0x1e5);
usleep(100000);
pcilib_write_register(ctx->pcilib, NULL, "control", 0x1e1);
}
//#endif /* DEBUG_HARDWARE */
// Benchmark
for (iter = 0; iter < iterations; iter++) {
memset(cmp, 0x13 + iter, size * sizeof(uint32_t));
//#ifdef DEBUG_HARDWARE
if (ctx->type == PCILIB_NWL_MODIFICATION_IPECAMERA) {
pcilib_write_register(ctx->pcilib, NULL, "control", 0x1e1);
}
//#endif /* DEBUG_HARDWARE */
gettimeofday(&start, NULL);
if (direction&PCILIB_DMA_TO_DEVICE) {
memcpy(buf, cmp, size * sizeof(uint32_t));
err = pcilib_write_dma(ctx->pcilib, writeid, addr, size * sizeof(uint32_t), buf, &bytes);
if ((err)||(bytes != size * sizeof(uint32_t))) {
error = "Write failed";
break;
}
}
//#ifdef DEBUG_HARDWARE
if (ctx->type == PCILIB_NWL_MODIFICATION_IPECAMERA) {
pcilib_write_register(ctx->pcilib, NULL, "control", 0x3e1);
}
//#endif /* DEBUG_HARDWARE */
memset(buf, 0, size * sizeof(uint32_t));
err = pcilib_read_dma(ctx->pcilib, readid, addr, size * sizeof(uint32_t), buf, &bytes);
gettimeofday(&cur, NULL);
us += ((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec));
if ((err)||(bytes != size * sizeof(uint32_t))) {
error = "Read failed";
break;
}
if (direction == PCILIB_DMA_BIDIRECTIONAL) {
res = memcmp(buf, cmp, size * sizeof(uint32_t));
if (res) {
for (i = 0; i < size; i++)
if (buf[i] != cmp[i]) break;
bytes = i;
printf("Expected: *%lx, Written at position %lu:", 0x13 + iter, bytes);
for (; (i < size)&&(i < (bytes + 16)); i++) {
if (((i - bytes)%8)==0) printf("\n");
printf("% 10lx", buf[i]);
}
printf("\n");
error = "Written and read values does not match";
break;
}
}
#ifdef DEBUG_HARDWARE
puts("====================================");
err = pcilib_read_register(ctx->pcilib, NULL, "reg9050", ®val);
printf("Status1: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9080", ®val);
printf("Start address: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9090", ®val);
printf("End address: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9100", ®val);
printf("Status2: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9110", ®val);
printf("Status3: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9160", ®val);
printf("Add_rd_ddr: %i 0x%lx\n", err, regval);
#endif /* DEBUG_HARDWARE */
}
#ifdef DEBUG_HARDWARE
puts("------------------------------------------------");
err = pcilib_read_register(ctx->pcilib, NULL, "reg9050", ®val);
printf("Status1: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9080", ®val);
printf("Start address: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9090", ®val);
printf("End address: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9100", ®val);
printf("Status2: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9110", ®val);
printf("Status3: %i 0x%lx\n", err, regval);
err = pcilib_read_register(ctx->pcilib, NULL, "reg9160", ®val);
printf("Add_rd_ddr: %i 0x%lx\n", err, regval);
#endif /* DEBUG_HARDWARE */
if (error) {
pcilib_warning("%s at iteration %i, error: %i, bytes: %zu", error, iter, err, bytes);
}
#ifdef NWL_GENERATE_DMA_IRQ
dma_nwl_disable_engine_irq(ctx, writeid);
dma_nwl_disable_engine_irq(ctx, readid);
#endif /* NWL_GENERATE_DMA_IRQ */
dma_nwl_stop_loopback(ctx);
__sync_synchronize();
if (direction == PCILIB_DMA_FROM_DEVICE) {
pcilib_skip_dma(ctx->pcilib, readid);
}
free(cmp);
free(buf);
return error?-1:(1. * size * sizeof(uint32_t) * iterations * 1000000) / (1024. * 1024. * us);
}
|
