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authorSuren A. Chilingaryan <csa@suren.me>2020-03-08 16:23:41 +0100
committerSuren A. Chilingaryan <csa@suren.me>2020-03-08 16:23:41 +0100
commit7b2e6168b049be9e7852b2d364d897592eff69fc (patch)
tree65b043a0d0583d03a55db697e228fa30ffb3061c /docs/hardware.txt
parent0fa60586c49c2ba10f1e24c6533ebf4980372f2f (diff)
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Fix 64-bit ids, ROOF ids are big-endian, skip incomplete datasets at the end and if with specified latency, try to reconstruct from desynchronized streams (harmful, debugging only)HEADmaster
Diffstat (limited to 'docs/hardware.txt')
-rw-r--r--docs/hardware.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/docs/hardware.txt b/docs/hardware.txt
index 50c3a0c..006829d 100644
--- a/docs/hardware.txt
+++ b/docs/hardware.txt
@@ -1,3 +1,4 @@
+ - The packet ids are 64-bit and in big-endian data format
- Jumbo frames are not currently supported, max packet size is 1500 bytes.
* The maximum number of samples per packet can be computed as
n = (1500 - header_size) / sample_size (pixels_per_module * bpp) i.e. 46 = | 1492 / 32 |
@@ -9,3 +10,4 @@
Questions
=========
- Do we need to compute 'flats' and 'darks' for each plane separately? Or just one set will work for all?
+ - How do FPGA syncrhonize IDs? Is it reliable. I currently have desync in receiving (but this could be caused by networking stack problems) \ No newline at end of file